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and btw basically it's about Intel vs AMD issue and they were always paying more to release soft for their CPUs and they had EU bans for this as well. And maybe Intel has implented some features that was used first in AMD instuction set, but they never tell this, because they act like this in other case. And i think it's important to show to many developers, that they may cheat like this for years, well, if those instructions are there really. When they release the game - it should work with many GPUs and everybody understand this - because it is customers, same thing is about CPU. VAlve has enough powers to check it and find the workaround, some other studios working with bought engine -they just can't. For example unrealengine games are still working with my CPU, so they got those workarounds prob. and this means they got to do some work.
And if you want to get closer it was Core2Duo/Quad with Penryn arch https://en.wikipedia.org/wiki/Penryn_(microprocessor)
and i7-900 https://en.wikipedia.org/wiki/List_of_Intel_Core_i7_processors
that supports those 4.2 both released in 2007-2008
it's just stupid
all they need is just to recompile with different instruction set compiler.
in fact they had to do this for much better CPUs also. becasue you are right 15 years has passed already, that's the work they should do these days. maybe this should be switched in game like changing shader-model (on-depends), but for VUlkan API vs DirectX - you got to switch exec file.
thanks for your reply
Coreinfo v3.6 - Dump information on system CPU and memory topology
Copyright (C) 2008-2022 Mark Russinovich
Sysinternals - www.sysinternals.com
AMD Phenom(tm) II X6 1090T Processor
AMD64 Family 16 Model 10 Stepping 0, AuthenticAMD
Microcode signature: 00000000
HTT * Multicore
CET - Supports Control Flow Enforcement Technology
Kernel CET - Kernel-mode CET Enabled
User CET - User-mode CET Allowed
HYPERVISOR * Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
SGX - Supports Intel SGX
NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS - Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT * Implements AMD MMX extensions
3DNOW * Supports 3DNow! instructions
3DNOWEXT * Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 - Supports Supplemental SIMD Extensions 3
SSE4a * Supports Streaming SIMDR Extensions 4a
SSE4.1 - Supports Streaming SIMD Extensions 4.1
SSE4.2 - Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX - Supports AVX instruction extensions
AVX2 - Supports AVX2 instruction extensions
AVX-512-F - Supports AVX-512 Foundation instructions
AVX-512-DQ - Supports AVX-512 double and quadword instructions
AVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF - Supports AVX-512 prefetch instructions
AVX-512-ER - Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD - Supports AVX-512 conflict detection instructions
AVX-512-BW - Supports AVX-512 byte and word instructions
AVX-512-VL - Supports AVX-512 vector length instructions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE - Supports XSAVE/XRSTOR instructions
OSXSAVE - Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR * Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ - Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS - Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM - Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR - Supports disabling task priority messages
EIST - Supports Enhanced Intel Speedstep
ACPI - Implements MSR for power management
TM - Implements thermal monitor circuitry
TM2 - Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE - Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 00000006 (Basic), 8000001B (Extended).
Maximum implemented address width: 48 bits (virtual), 48 bits (physical).
https://learn.microsoft.com/en-us/sysinternals/downloads/coreinfo
Sorry bro but you won't be able to play CS2 until you upgrade
well, ok * means support, this program should just show the supported instructions and the list of unsupported elsewhere
But it's comparable to i7-920 https://www.cpu-world.com/Compare/691/AMD_Phenom_II_X6_2.8_GHz_(2D284100K6D30)_vs_Intel_Core_i7_Mobile_Extreme_Edition_i7-2920XM.html
basically it's like you ask from everyone to use only salted water to buy and never drink with sugar> because they got "intel virtual machine" but amd has "secure virtual machine"
and when you see one instructions "-" field, the other CPU has the "+" there
Amd has 3dNOW and intel has Advanced Vector Xtensions
They may not support the M1 cpu, because there's no Windows and DirectX there, but they will prob. and i'm not the only one with such CPU, if they really mean that they've produced a game for same old CPUs
and yes, i got the i7-3400 in the other room, but i dont want to use it
and E8400 in another, maybe it would work with it too, also made for different stuff.
i'm not the only one with such CPU around the world it's about most used CPU for some time and it's more powerful than those quad intels.
And if they will produce that amd-optimized exe - all the AMD CPU users will get a major boost, that they never had before in games, because it was always made for intel.
And it's about the same sh** people had with hello Anti-Lag+ , because they did for Nvidia.
And it's not like ps2 vs ps5, it's like xbox360 vs ps3, or xbox one vs ps4, but it's not SEGA and it's not ps2 vs ps3 ok? it's the same release date years.
And maybe you still didn't get that, but they will sell this engine to other studios after fixing all bugs and they will also have this problem.
for devs what you really should do https://forums.unrealengine.com/t/cpu-gpu-profiler/1338092