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they clip off or disable the bad parts
but now they are using chiplets, smaller pieces and putting them together, to build the best cpu bins they can sell
with the correct drivers windows can set background tasks for the slower cores, but still uses buss bandwidth and ram and other resources, that could make it slow down other tasks
if you want to disable the e cores you can do that in bios
not going to spend money on something that is purposefully made to be low performance... why would I buy that ever ?
But it's not what happens here. The e-cores are not p-cores with things missing. They're actually different thing. So you can't make an e-core from a defective p-core.
Intel also currently has monolithic chips still. They're not MCMs (multi chip modules) like AMD has been since Ryzen. Intel will be going to their equivalent of chiplets, called tiles, with the 15th or 16th generation, but they're monolithic for now.
CPUs used to be pretty much single core, until it became impractical to improve their speed & performance fast enough. The solution was more cores.
You have a completely incorrect understanding of this. Intel CPUs with e-cores are not "chiplets"; which is a term describing a packaging method of mounting multiple processor dies onto a chip package. All of the Intel CPUs with e-cores have been monolithic designs, meaning they are all one die, not multiple "chiplets" on a package. Being able to disable something in BIOS/UEFI doesn't have anything to do with it being a different die; you can also disable hyperthreading / Symmetric Multi-Threading (SMT).
Further fusing off bad silicon is a process to reduce waste and improve yields in manufacturing; that hasn't ever been done as you're suggesting to change the makeup of a compute core. It is a result of engineers designing a scalable architecture so that when there is a defect, they are able to fuse off the corresponding unit where the defect is while retaining the functionality of the remaining units. E.g. making an 8-core die into a 6-core die.
Again, because not everything your computer is doing requires, or even really benefits from, high-performance more complex compute cores. This coupled with physics and chemistry being part of reality are why this is done.
There are a plethora of design constraints including thermal, electrical, electromagnetic, and more importantly silicon die space which chip engineers need to design around and make tradeoffs within those constraints. Die space in particular when dealing with a monolithic design is extremely important as we don't have the means to make perfect lithography and defects happen (as noted above). The larger the die, the fewer dies-per-wafer and the higher the likely hood of having a defect within a die; thus reducing the yield. Beyond limitations in die space power and temperature constraints are also another very real limitation. This is why you will see that as core-count increases, the clock speed of those cores decreases (in a monolithic design).
If you can fit 4x e-cores in the same physical die space as 1x p-core, and the power and thermal requirements for those 4x e-cores is less than the 1x p-core, then for a large amount of workloads you will be yielding substantially higher aggregate performance. Which is what the case is here; see the die-block-diagram below.
Raptor Lake CPU Die[en.wikipedia.org]
They are able to fit 16x e-cores in about the same die space as 4x p-cores, and those e-cores are able to operate within a lower power and thermal budget than if they had just replaced them with 4x additional p-cores. Which for a large amount of OS and general purpose tasking will result in substantially better overall performance. You will see AMD implementing this same approach in the near future, just as you will see Intel moving to an MCM package in the near future.
The challenge with this non-homogenious microarchitecture design is that software needs to be aware of the differences between the differing compute resources otherwise you'll end up shoving an process into a core which doesn't support the instruction required by the process. This isn't something new or something Intel invented, and I'd highly suspect you are already "buying that" as you likely have a smart phone that is using an ARM architecture which employs a big.LITTLE design.
Just for clarity, Intel does already have MCM designs but those are not in the consumer "Core" CPU product line yet (as you've pointed out). Intel plans to move to MCM / Tiles with Meteor Lake which is also 14th Gen (this year). For 14th Gen they are expected to have the desktop CPUs based on Raptor Lake-SR (e.g. the Raptor Lake-S "Refresh"), the mobile/"Ultrabook" CPUs based on Meteor Lake-P, and they are also expected to have a Raptor Lake-PR (e.g. a Raptor Lake-P "Refresh") for low-end and "gaming" portable devices that will also be 14th Gen. With 15th Gen we should see both desktop and mobile move to MCM/Tiles with Arrow Lake-S and Arrow Lake-P. And with 16th Gen improving on the Tile-based designs by moving to a substantially more advanced Foveros 3D stacking for both Lunar Lake-S and Lunar Lake-P designs.
its super easy for them to disable parts/performance and flag each core as p or e
on paper or diagrams its easy to make them look smaller since more parts on them are not used
they are dealing with super tiny, errors are way more common than you think
again, not all wafers produce 100% i9 cpus, they also make enough i7/i5/i3/pentium g and laptop cpu
also ones with bad or lower performing igpu get the f with those parts disabled
I already gave you the links to the Wikis on the different core microartectures and the link to the 13th gen Core i9 die image with the blocks overlayed ontop.
You clearly do not understand how CPUs are made. That isn't an "on paper we make them look smaller", that is an image of the actual CPU die.
Here it is without the blocks overlayed
13900K Die[en.wikipedia.org]
Yes, the E-cores aren't crippled P-cores.
https://en.wikipedia.org/wiki/Gracemont_(microarchitecture)
https://en.wikipedia.org/wiki/Golden_Cove#Raptor_Cove
The e-cores and p-cores are physically different.
I already gave 'em all of those ^ up there ;) lol I linked the one without the block-diagram overlay since they seemed to think "they make them look smaller on paper".
You can clearly see from the die shot that they are two completely different core designs, even if you disregard that we've already pointed out that the e-cores are Gracemonte and the (current 13th gen) p-cores are Raptor Cove.