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Working as intended. You do have four cores.
AMD calls physical core "module". FX-770K based on Steamroller architecture which made these logical cores much more independent than they were in Piledriver. Every logical core got its own decoder (main CISC CPU pipeline stages is fetch, decode, register renaming, dispatch/issue, execution, write and retirement). Before Steamroller both logical cores used the same in-order frondend and shared physical core resources in SMT way (each thread got resources every other cycle).
Thus, task manager is right.
Many places including these threads demonstarate well that the confusing people works fine... :(
If you want to compare FX processors for something else, ignore the "core" column, ask the "module" count and compare that with other processors' core count. You can notice that proper programs also mark them with M instead of C.
L2 cache and FPU are shared between two cores in one block. Intel cores are more capable and have their own I guess both L2 cache and FPU.
Common no knowledge crap however make people say so. Maybe because that would explain the lower performance for them.
If you want to understand why it's slower then you need to look into what's actually different on them beyond the module part.
Bulldozer: 2 ALU, 2 AGU / core 16 kB L1 four-way cache / core, 4 64 bit ADD and 4 64 bit MAC up to 2 MB L2 cache shared between two cores
Steamroller: I'm too lazy to check up all the details in general for any of them, still 4 integer units / core, I assume 2 ALU and 2 AGU there too, the shared FPU is 2 128 bit FMAC (both multiplier and adder.)
Kaby lake: 4 ALU, 4? AGU / core, 32 kB 8-way associative data + 32 kB instruction L1 cache, 256 kB 4-way associative L2 cache / core, 2 MB 16-way associative L3 cache / core. 2 256 bit ADD + 2 256 bit MUL.
The AMD isn't dual core. It's cores just have half the integer stuff though and each two cores share FPU and L2 cache.
Edit: If it actually was 2 cores then feel free to reason your way around why the single core performance is so weak .. And why it does better with multi-threaded tasks. The AMD processor actually WILL run four threads whereas an i3 with HT kinda will do it when it got the possibility. Going from 2 to 4 threads on the AMD chip with integer tasks should about double the performance whereas on the i3 it won't. And if the task just use one or two threads or are limited in performance by it then the i3 will run it just fine due to as capable cores as the more expensive chips and its high frequency while the AMD chip won't because it's not a capable two core chip it's a four core chip and two cores will just sit there not being able to help.
Edit 2: It's likely easier to come up with "oh but it's really just a 2 core chip!" to explain the difference in capability. Since it's there and it make no sense if the number of cores (or clock frequency) is all you look at. But it's wrong. It has four weaker integer cores.
https://www.youtube.com/watch?v=yRWsoWWtXA8
Why ppl buy cpus lower than the FX6300 (that overclocks) and the G4560 is beyond me, FM1/2 had a market but not in the dedicated gpu gaming market.
The x4 6xx and x3 4xx where also cheap Athlons no L3 cache they had there place but gaming wasn't it.
Arguing about whether it has 2 or 4 cores threads is pointless because it is considered crap.
Hopefully ppl will do more research when buying cpus in the future because my guess about Ryzen 3 is it's going to be a budget piece of crap I hope I'm wrong but I don't see it being stellar the ipc will need to shoot up.
Steamroller L2 cache 2 MB / block, 16-way, 19 clocks latency, 1 read per 4 periods, writes 1 per 6 periods.
Kaby lake L2 cache 256 kB / core latency 12 cycles, 4-way, L3 cache 2 MB / core 16-way latency 38 cycles.
Fetched code goes through pipeline to decoder which runs the same way - one cycle it decodes (translate x86 commands to RISC-like uops) for one thread, next to another.
That is what called SMT. After that all uops goes into single out-of-order backend where they can be executed in arbitrary order.
How Piledriver pipeline works?
It also has single fetch unit which gets code for the threads every other clock cycle - first cycle to one thread, second to another. Exactly the same way as Core i does (i3 or i7 - doesn't matter, all of them have the same cores).
After that fetched code goes to decoder, but Piledriver has only 1 decoder for both logical cores so process repeats. Do you see there is no difference between Intel and AMD approach
yet?
The difference appears only in RISC-like backend.
Core i and Ryzen use more complex approach: they have single pipeline for both thread so every thread can use all resoources of physical CPU when they need them.
Piledrives in turn has far more simpler design - it has TWO different out-of-order pipelines and execution units dedicated to each of logical cores. So, even when core runs only one thread this thread have access only to half of ALU/AGU anyway.
Why AMD did so? Because pretty often result of first executed command needs to execute second. And you need to transfer this result from one execution unit output port to another EU input port without delay. For this task CPU has so-called bypass network. To make this network simpler AMD limited its capabilities - it can move operands only between half of EUs for each logical core.
As a result each logical core becomes weaker (ever thread can use only 2 integer ALU and 2 AGU for the thread), but Piledriver gets less penalty for running 2 thread on the same core.
When you run 2 threads on 2 physical cores you should get 200% of single core performance.
Core i allows gains about 140% single-thread performance when runs 2 thread in HT mode.
Piledriver have 170%. Do you see that this percentage more than HT, but less than 2 real cores?