BuddaZero 23 listopada 2016 o 1:08
RAM Suggestions Please
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SundownKid 23 listopada 2016 o 2:58 
As far as I know, there is no difference between the cheapest RAM on the market that is the same speed and the pricier kind.
Początkowo opublikowane przez SundownKid:
As far as I know, there is no difference between the cheapest RAM on the market that is the same speed and the pricier kind.
Except pretty much every specification of the RAM.

Including but not limited to:

XMP Setting Load XMP settings to overclock the DDR memory and perform beyond standard specifications. DRAM Reference Clock Select Auto for optimized settings.
DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically.
DRAM Frequency OC Preset If the DRAM frequency is selected, the corresponding DRAM and BCLK frequency for overclocking will be set.
Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP) O RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge: The number of clock cycles required between the issuing of the precharge command and opening the next row.
RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command.
Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued.

Secondary Timing Write Recovery Time (tWR) The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged.
Refresh Cycle Time (tRFC) The number of clocks from a Refresh command until the first Activate command to the same rank.
RAS to RAS Delay (tRRD_L) The number of clocks between two rows activated in different banks of the same rank. RAS to RAS Delay (tRRD_S) The number of clocks between two rows activated in different banks of the same rank.
Write to Read Delay (tWTR_L) The number of clocks between the last valid write operation and the next read command to the same internal bank.
Write to Read Delay (tWTR_S) The number of clocks between the last valid write operation and the next read command to the same internal bank.
Read to Precharge (tRTP) The number of clocks that are inserted between a read command to a row precharge command to the same rank.
Four Activate Window (tFAW) The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL) Configure CAS Write Latency.
Third Timing tREFI Configure refresh cycles at an average periodic interval.

tCKE Configure the period of time the DDR4 initiates a minimum of one refresh command internally once it enters Self-Refresh mode.
tRDRD_sg Configure between module read to read delay.
tRDRD_dg Configure between module read to read delay.
tRDRD_dr Configure between module read to read delay.
tRDRD_dd Configure between module read to read delay.
tRDWR_sg Configure between module read to write delay.
tRDWR_dg Configure between module read to write delay.
tRDWR_dr Configure between module read to write delay.
tRDWR_dd Configure between module read to write delay.
tWRRD_sg Configure between module write to read delay.
tWRRD_dg Configure between module write to read delay.
tWRRD_dr Configure between module write to read delay.
tWRRD_dd Configure between module write to read delay.

tWRWR_sg Configure between module write to write delay.
tWRWR_dg Configure between module write to write delay.
tWRWR_dr Configure between module write to write delay.
tWRWR_dd Configure between module write to write delay.
RTL (CH A) Configure round trip latency for channel A.
RTL (CH B) Configure round trip latency for channel B.
IO-L (CH A) Configure IO latency for channel A.
IO-L (CH B) Configure IO latency for channel B.
Fourth Timing twRPRE Configure twRPRE.
Write_Early_ODT Configure Write_Early_ODT.
tAONPD Configure tAONPD.
tXP Configure tXP.
tXPDLL Configure tXPDLL.

tPRPDEN Configure tPRPDEN.
tRDPDEN Configure tRDPDEN.
twRPDEN Configure twRPDEN.
OREF_RI Configure OREF_RI.
tREFIx9 Configure tREFIx9.
txSDLL Configure txSDLL.
txs_offset Configure txs_offset.
tZQOPER Configure tZQOPER.
tMOD Configure tMOD.
ZQCS_period Configure ZQCS_period.
tZQCS Configure tZQCS.
Advanced Setting ODT WR (CH A) Configure the memory on die termination resistors' WR for channel A.
ODT WR (CH B) Configure the memory on die termination resistors' WR for channel B.

ODT PARK (CH A) Configure the memory on die termination resistors' PARK for channel A.
ODT PARK (CH B) Configure the memory on die termination resistors' PARK for channel B.
ODT NOM (CH A) Use this to change ODT (CH A) Auto/Manual settings. The default is [Auto]. ODT NOM (CH B) Use this to change ODT (CH B) Auto/Manual settings. The default is [Auto].
MRC Fast Boot Enable Memory Fast Boot to skip DRAM memory training for booting faster.
Voltage Configuration Power Saving Mode
Enable Power Saving Mode to reduce power consumption. CPU Vcore Voltage Configure the voltage for the CPU Vcore.
SET OV This funtion allows override of normal operation to overvoltage of 2.455.
DRAM Voltage Use this to configure DRAM Voltage. The default value is [Auto].
DRAM Activating Power Supply Configure the voltage for the DRAM Activating Power Supply.
PCH +1.0 Voltage Configure the chipset voltage (1.0V).
VCCIO Voltage Configure the voltage for the VCCIO.
VCC PLL Voltage Configure the chipset voltage (1.50V).

VCCSA Voltage Configure the voltage for the VCCSA.


... and much more!
Ostatnio edytowany przez: [wan-clan.org] Gordy Freeman; 23 listopada 2016 o 3:16
Początkowo opublikowane przez Gordy:
Początkowo opublikowane przez SundownKid:
As far as I know, there is no difference between the cheapest RAM on the market that is the same speed and the pricier kind.
Except pretty much every specification of the RAM.

Including but not limited to:

XMP Setting Load XMP settings to overclock the DDR memory and perform beyond standard specifications. DRAM Reference Clock Select Auto for optimized settings.
DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically.
DRAM Frequency OC Preset If the DRAM frequency is selected, the corresponding DRAM and BCLK frequency for overclocking will be set.
Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP) O RAS# to CAS# Delay : The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge: The number of clock cycles required between the issuing of the precharge command and opening the next row.
RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command.
Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued.

Secondary Timing Write Recovery Time (tWR) The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged.
Refresh Cycle Time (tRFC) The number of clocks from a Refresh command until the first Activate command to the same rank.
RAS to RAS Delay (tRRD_L) The number of clocks between two rows activated in different banks of the same rank. RAS to RAS Delay (tRRD_S) The number of clocks between two rows activated in different banks of the same rank.
Write to Read Delay (tWTR_L) The number of clocks between the last valid write operation and the next read command to the same internal bank.
Write to Read Delay (tWTR_S) The number of clocks between the last valid write operation and the next read command to the same internal bank.
Read to Precharge (tRTP) The number of clocks that are inserted between a read command to a row precharge command to the same rank.
Four Activate Window (tFAW) The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL) Configure CAS Write Latency.
Third Timing tREFI Configure refresh cycles at an average periodic interval.

tCKE Configure the period of time the DDR4 initiates a minimum of one refresh command internally once it enters Self-Refresh mode.
tRDRD_sg Configure between module read to read delay.
tRDRD_dg Configure between module read to read delay.
tRDRD_dr Configure between module read to read delay.
tRDRD_dd Configure between module read to read delay.
tRDWR_sg Configure between module read to write delay.
tRDWR_dg Configure between module read to write delay.
tRDWR_dr Configure between module read to write delay.
tRDWR_dd Configure between module read to write delay.
tWRRD_sg Configure between module write to read delay.
tWRRD_dg Configure between module write to read delay.
tWRRD_dr Configure between module write to read delay.
tWRRD_dd Configure between module write to read delay.

tWRWR_sg Configure between module write to write delay.
tWRWR_dg Configure between module write to write delay.
tWRWR_dr Configure between module write to write delay.
tWRWR_dd Configure between module write to write delay.
RTL (CH A) Configure round trip latency for channel A.
RTL (CH B) Configure round trip latency for channel B.
IO-L (CH A) Configure IO latency for channel A.
IO-L (CH B) Configure IO latency for channel B.
Fourth Timing twRPRE Configure twRPRE.
Write_Early_ODT Configure Write_Early_ODT.
tAONPD Configure tAONPD.
tXP Configure tXP.
tXPDLL Configure tXPDLL.

tPRPDEN Configure tPRPDEN.
tRDPDEN Configure tRDPDEN.
twRPDEN Configure twRPDEN.
OREF_RI Configure OREF_RI.
tREFIx9 Configure tREFIx9.
txSDLL Configure txSDLL.
txs_offset Configure txs_offset.
tZQOPER Configure tZQOPER.
tMOD Configure tMOD.
ZQCS_period Configure ZQCS_period.
tZQCS Configure tZQCS.
Advanced Setting ODT WR (CH A) Configure the memory on die termination resistors' WR for channel A.
ODT WR (CH B) Configure the memory on die termination resistors' WR for channel B.

ODT PARK (CH A) Configure the memory on die termination resistors' PARK for channel A.
ODT PARK (CH B) Configure the memory on die termination resistors' PARK for channel B.
ODT NOM (CH A) Use this to change ODT (CH A) Auto/Manual settings. The default is [Auto]. ODT NOM (CH B) Use this to change ODT (CH B) Auto/Manual settings. The default is [Auto].
MRC Fast Boot Enable Memory Fast Boot to skip DRAM memory training for booting faster.
Voltage Configuration Power Saving Mode
Enable Power Saving Mode to reduce power consumption. CPU Vcore Voltage Configure the voltage for the CPU Vcore.
SET OV This funtion allows override of normal operation to overvoltage of 2.455.
DRAM Voltage Use this to configure DRAM Voltage. The default value is [Auto].
DRAM Activating Power Supply Configure the voltage for the DRAM Activating Power Supply.
PCH +1.0 Voltage Configure the chipset voltage (1.0V).
VCCIO Voltage Configure the voltage for the VCCIO.
VCC PLL Voltage Configure the chipset voltage (1.50V).

VCCSA Voltage Configure the voltage for the VCCSA.


... and much more!
oh my gawddddd!
i am buying a pizza instead of a memory upgrade...
Back in the -old- days TomsHardware (when it was still owned by Tom Pabst) published an article that explained why high performance RAM was 'sometimes' worth the extra investment.

That information is long gone, but it remains in the heads of many hardware enthusiasts.
[☥] - CJ - 23 listopada 2016 o 3:54 
Dominator is ok..

But i loves me some Vengeance.
Had nothing but good times with the vengance brand.
BuddaZero 23 listopada 2016 o 12:34 
Thank you everyone, I ended up choosing this:

http://www.newegg.com/Product/Product.aspx?Item=N82E16820232329

You guys have a good thanksgiving!

Best,

Budda
Sphereman 23 listopada 2016 o 15:11 
64 gb of ram is SO overkill. Why even bother to use that much in your pc?
BuddaZero 23 listopada 2016 o 16:41 
Początkowo opublikowane przez Mastertroller:
64 gb of ram is SO overkill. Why even bother to use that much in your pc?

I'm a video editor, graphic designer, and I do animation. 16gb wasn't enough. 32 gb looks enough but on the safe side-I'm going 64gb so I can render my stuff with ease.
BuddaZero 27 listopada 2016 o 6:45 
Hey guys-build went great, couldn't be happier. The only problem I've come across was my Windows 10 Pro 64 bit system not recognizing my 64gb of ram. It only reads 16gb. My mother board reads 64gb with it's 3200mhz, so is windows 10 still using it-but doesn't know it?
[☥] - CJ - 27 listopada 2016 o 13:57 
So, under System and Task Manager its only showing 16GB?

Using CPU-Z, does it only show 1 RAM stick as being installed?
BuddaZero 27 listopada 2016 o 14:28 
Początkowo opublikowane przez ☥ - CJ -:
So, under System and Task Manager its only showing 16GB?

Using CPU-Z, does it only show 1 RAM stick as being installed?

It now shows 32 gb of ram now. but still I have 64gb.

Under task manager it says: Slots Used - 2 Out of 8. I guess Windows 10 isn't reading the other 2, cause I installed 4.

I've heard of CPU-Z, I'm fairly new to PC building, so I download it. Do I just download any version of windows 10 from the site? Want to make sure I get the right one.

Thank you!

Best,

Budda
Bad 💀 Motha 27 listopada 2016 o 16:11 
First check the RAM in the BIOS, should all show in there if properly installed.

As for Win10, of course, get that from Microsoft and make your own usb flash drive media.
https://www.microsoft.com/en-us/software-download/windows10
BuddaZero 27 listopada 2016 o 16:19 
Początkowo opublikowane przez Bad-Motha:
First check the RAM in the BIOS, should all show in there if properly installed.

As for Win10, of course, get that from Microsoft and make your own usb flash drive media.
https://www.microsoft.com/en-us/software-download/windows10

Sorry I worded that last sentence wrong. I meant the windos 10 version of CPU-Z. I'm trippled checked, and I have all the updates, and I even checked the BIOS. All the ram is there, including its speed. It had a XMP profile.
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