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Also this is Microcontrollers, not UNIX :D
Say you're using the P wires to communicate. The left one gets out of its "slp 1" and the right MC as well. The left one calculates a number to send. Say it wants to add 5 to the accumulator and then send it. So it has a "add 5" and a "mov acc p1". The right one has a "mov p0 dat". But it will not read the correct value, as it reads before the left MC sends the value. You need to sync that design with NOPs or otherwise.
On the other hand, if you use the X wires to communicate in the same situation, you can just mov the value onto X3 on the left one and read from X0 on the right one without thinking about which one is first. If the reading one is first, it will wait until a value gets written and then read it and continue (during the same time unit / cycle). If the writing one is first, it will block until someone on the wire is ready to read and only then will it send the value and continue (not beyond the same time unit / cycle).
[nod] I was hoping for power and instruction efficiency here. Having to allocate an extra instruction to achieve the expected blocking behavior (sleep until I/O is available) is unfortunate in the application I was using it for.
Blocking on I/O can't last longer than the current cycle, got it. That probably should be worked into the manual?
Sure, if you think it's not perfectly clear from the manual, you should report it as a bug via email.