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Order is random, so you will need to use NOP to get the timing right - one xbus packet will wake
all listening (with SLX) MCs, but only one of them will be able to read the packet.
Alternatively, you could use simple IO which can be read multile times but which cannot wake MCs.
Ah, thanks for the explanation, that makes sense. With only one XBUS packet able to be read, I'll just have to route that data through a couple of circuits.
The simple IO seems like it could accomplish what I want, but getting the timing right seems trickier.
overflowing the address for a ram make the pointer wrap around. ie 14 becomes 0
Plus, I just used the tcp command for the first time. I'm starting to see how useful it can be.
I'll keep that RAM/ROM trick in mind for the future, thanks.
http://images.akamai.steamusercontent.com/ugc/99478222108424851/5CC81A21220BA9BFFE0B8ED47F67BE83C9F44100/