Why are flip flops represented with NOT gates?

[Ramshackle]

I get that there are a bunch of ways to build a flip-flop electronically, but in this boolean representation, why are flip flops built with not gates rather than NOR?
For someone unfamiliar with the circuitry, seeing the outputs of the NOT gate and the Input node come together at the input of the other NOT gate obscures the underlying logic. As far as they know, the behaviour of combining the signals is undefined.
For someone who is familiar with the circuitry it kinda screams potential short circuit.
Anyway, Im only an hour in, but really enjoying the game.

[uNiels 💗]

I don't see a huge problem with this solution. And it is simpler to understand if you haven't seen an RS latch before.

There certainly isn't a short-circuit (or, more appropriately in the digital signal world, conflicting signals of the same strength).

If you apply a 0, 1 signal, then the first inverter inverts the 0 to 1, which connects to the second input, which is already 1, so no conflict there. Analogously for the other inverter, just 0/1 swapped.

If you apply a 1, 0 signal, then the first inverter inverts the 1 to 0, which connects to the second input, which is already 0, so no conflict there.

If you apply a 0, 0 signal, that works, as in this game the 0 signals are weak and the 1 signals are strong. That's allowed. Basically think of the 0 signal as the same as a big-valued pull down resistor would provide. While the 1 signal connects directly to VCC.

A 1, 1 signal is forbidden anyway.

The only problems with this design I see is that they interconnect inputs and outputs. In the real world, you would probably need to buffer the inputs to use this kind of component in a design.

[Ramshackle]

Yeah I suppose I just had it drilled into me that you don't connect digital outputs together unless you have a really good reason to do so.
However these gates are coded, you're right that logic low is weak, but that's not explicitly stated. You could make the same circuit with NOT gates and inputs that connect logic high and low to the power rails, and then you really do get a short when you latch/load. So whether this circuit actually works or catches fire depends entirely on the specifics of the components you use, when they should be interchangeable.
If you are relying on the fact that low is weak here, then the truth table for the NOT gate with two inputs becomes that of a NOR gate. In which case, just use a NOR gate. Same result, without the unstated assumptions and potential confusion.
It's a minor detail for sure, but its also bad design in a game that seems to be educational.

[Ramshackle]

Also I just noticed that the flip flop circuit is the background to this forum, so I can't be the only person who is going to notice this.

[Ramshackle]

Also also: I haven't checked in the game, but if there is nothing stopping you from combining outputs like this, then some people are going to learn that there is no reason to use a NOR gate, you can just overload a NOT. And there is not reason to use a OR gate, you just overload the input of the next gate. And that's going to lead to a lot of really bad circuits working in this game that really shouldn't.

[uNiels 💗]

Originally posted by Roam:

...
Same result, without the unstated assumptions and potential confusion.
It's a minor detail for sure, but its also bad design in a game that seems to be educational.

Regarding unstated assumptions ... they aren't mere assumptions. It's a conclusion that follows from seeing how the game behaves. You will see in later levels that you are allowed to drive a wire from multiple outputs and the 1 always wins. Hence it follows that 1 must be strong and 0 must be weak. It's obviously a simplification. In the real world you would usually use tri-state or open collector designs instead.

It definitely possible to design gates in with just 2 states and the low voltage state being a weak signal in the real world. It's just highly impractical, that's why it's done differently.

And well, yes, you're allowed to make an OR gate in the game with just interconnecting wires, but it's not equivalent to an OR gate made with gates. There's an issue concerning that regarding the scoring of the delay (same for the buffer circuit), which I brought up in the game's forum on the game's own web-site already.

But you will see multiple signals driving one wire theme a lot in this game, especially with 8-bit buses, so better make your peace with it.

[reinderien]

There's.. a lot to unpack here. First: I hope that

> better make your peace with it

isn't the author's response on most topics; otherwise what would be the point of early release?

Anyway, I think that "strong pullups, weak pulldowns" (open emitter) is fine, and even having this as an unstated assumption is fine. What _isn't_ fine is never demonstrating this at all. The game teaches all concepts by demonstration. In around the time that the game demonstrates circular dependencies, it should demonstrate output contention. This would fit perfectly with the ethos of the game and would add crucial context to later levels that's currently altogether missing. The Tangled Gates and one-way levels make absolutely no sense without this.

[noob_Lurker]

Originally posted by Roam:

Also also: I haven't checked in the game, but if there is nothing stopping you from combining outputs like this, then some people are going to learn that there is no reason to use a NOR gate, you can just overload a NOT. And there is not reason to use a OR gate, you just overload the input of the next gate. And that's going to lead to a lot of really bad circuits working in this game that really shouldn't.

Sometimes they disallow such contacts since it would create a feedback loop (and the message shown is "Circular dependency - The output of a component leads back to its own input."), but if the signals are independent, they can make contact at the input of a NOT gate... presumably allowed in order to reward efficient use of space? idk.

[uNiels 💗]

Originally posted by reinderien:

There's.. a lot to unpack here. First: I hope that

> better make your peace with it

isn't the author's response on most topics; otherwise what would be the point of early release?

No, it's my personal response and opinion.

I certainly don't expect the complete design decision of the game to be thrown over board and replaced by something else.

Originally posted by reinderien:

Anyway, I think that "strong pullups, weak pulldowns" (open emitter) is fine, and even having this as an unstated assumption is fine. What _isn't_ fine is never demonstrating this at all. The game teaches all concepts by demonstration. In around the time that the game demonstrates circular dependencies, it should demonstrate output contention. This would fit perfectly with the ethos of the game and would add crucial context to later levels that's currently altogether missing.

That's fair and I would recommend you make a suggestion to that effect if you want it. Maybe at a later date, when the game-not-working-under-these-circumstances bugs have been taken care of, or even now, at your own discretion. Preferably at some place where the author sees it and take note of it.

FWIW, circular dependencies can cause more problems than just bus contention. Especially in the context of this game, which - as far as I can see - isn't prepared to model the timing and feedback loop nuances that go with it.

Originally posted by reinderien:

The Tangled Gates and one-way levels make absolutely no sense without this.

I don't think so. The buffer does definitely make sense, both in the context of this game and in the real world. In this game, you can interconnect wires to form an OR function (due to the strong 1 and weak 0). If you aren't careful with that, a 1 from one side of that connection can undesirably drive preceding parts of your design on the other side of that connection if there are more inputs of other components connected on that wire. In effect, its function would then deviate from that of an OR cleanly built with an OR gate. To solve that problem, you can either replace it with a proper OR gate, or you can place buffer gates strategically (one is often sufficient). So it does make sense.

While in the real world a buffer can be used to prevent bus contention in a strict sense (as opposed to the game, where it cannot, because there is none), it can also be used to prevent undesirable behaviour (that isn't bus contention) in a way analogous to the game.

Not sure why you think the Tangled Gates level makes no sense without this. It certainly works the way the game presents it and it can be made to work in the same way in the real world if you use NOT gates with a strong 1 and a weak L and make sure that whatever is on its inputs is also either strong 1 or weak L and buffer them properly, if necessary.

It presents the same working principle as an SR latch made from NOR gates, except in the invalid state, but that's invalid anyways and the game doesn't go into detail about the invalid state.

[Ramshackle]

I suppose my objection boils down to this: If you are just representing a circuit with logic gates, its function (at a low enough speed) should be entirely independent of the physical hardware. Someone could actually build one of these using vacuum tubes, relays, FPGA, CMOS packages on a breadboard, minecraft redstone, whatever and it will work. Combining outputs breaks that. The behaviour becomes dependant on something that is not included in the schematic.

[reinderien]

Originally posted by Roam:

If you are just representing a circuit with logic gates, its function (at a low enough speed) should be entirely independent of the physical hardware. Someone could actually build one of these using vacuum tubes, relays, FPGA, CMOS packages on a breadboard, minecraft redstone, whatever and it will work. Combining outputs breaks that. The behaviour becomes dependant on something that is not included in the schematic.

The author had to choose what to do with output contention. Either 0 wins, 1 wins, or the circuit is disallowed. "0 wins" is a common and entirely feasible configuration - NMOS-side open drain/open collector - and "could actually be built". "1 wins" can't be built because no one offers PMOS-side open-drain gates as standard; you'd have to go down to the transistor or relay level for this to be possible.

All of this is to say:

Originally posted by Roam:

Combining outputs breaks that.

is not strictly true. Defining behaviour of combining outputs in the way that the author has in this game mostly breaks that.